Digital Design & Verilog HDL

The Digital Design & Verilog HDL programme is a beginner-friendly training course designed to introduce participants to the fundamentals of digital electronics and hardware design using Verilog Hardware Description Language (HDL). This hands-on programme provides practical exposure to semiconductor industry workflows, covering combinational and sequential logic design, finite state machines (FSM), simulation testbenches, and functional verification techniques. Participants will learn how to design, simulate, debug, and validate digital circuits through practical exercises and real-world examples. Suitable for engineering students, fresh graduates, and beginners interested in FPGA, digital IC design, and verification engineering, the programme equips learners with essential industry-relevant skills for entry-level semiconductor engineering roles. The training duration is 3 days (21 hours).